Quick start

Debug a testbench with F5#

1. Open a folder with your VHDL sources. To follow along, open examples/counter from the extension’s repository: a 4-bit counter and its testbench.

2. Open the testbench and press F5, or click Debug Current File as Testbench in the editor title.

   No launch.json is needed. The extension analyses every *.vhd/*.vhdl file of the folder and elaborates the entity of the open file. With a workspace file it uses the file’s sources and testbenches instead.

3. The simulation pauses at 0 fs and the signal viewer opens beside the editor.

From here:

• Click in the gutter of a process to set a breakpoint, then press Continue.
• Type run 100 ns in the Debug Console to advance simulated time.
• Press Ctrl+F10 (Step Time) to jump to the next time with activity.
• Press Ctrl+Shift+F10 to step back.

counter_tb.vhdl HDL Studio Signals

countercounter_tb.vhdl

GHDL: counter_tb @ 160 nsLn 39, Col 5VHDLHDL Studio 1.0.4

Look at the signals#

The left pane of the viewer is the design hierarchy; expanding a scope adds its signals. Click to place the cursor, and the values in the left pane become the values at the cursor. F fits the whole run, and L toggles Live to follow the simulation. More in The signal viewer.

Run without the debugger#

HDL Studio: Simulate Current File with Live Signals runs the testbench with the viewer but without the debugger. From a terminal, hdl run simulates headless and records a .ghw file:

hdl run counter_tb
hdl signals --at 50ns --filter count

See The hdl command line.

Next steps#

• Describe your project once in a workspace file.
• Learn the debugger and time travel.
• Take a design to hardware with the Vivado flow.