The Vivado flow

Setting up#

xvhdl, xelab and xsim are taken from the same bin directory, and hw_server from Vivado/bin or the Vitis/bin of the same release. When Vivado is missing, the dashboard and the Flow view say “Vivado not found” with a link to the settings.

Constraints from a board#

HDL Studio: Generate Constraints from Board… writes constraints/<board>.xdc with the system clock, a reset button and the first LED for the ports your top entity has. It also adds the file, the part and the board to the workspace file. The pins are copied from Digilent’s master constraints files for these boards:

Basys 3 · Arty A7-35 and A7-100 · Nexys A7-100T · Zybo Z7-20 · Cmod S7-25

HDL Studio: Flow

arty-a7blink · xc7a35ticsg324-1L

Vivado 2026.1synth · impl · bitstreamWNS +7.21 nsHDL Studio 1.0.4

Stages#

Each stage is a row of the Flow view and a VS Code task of type hdl, which .vscode/tasks.json may also use:

{ "type": "hdl", "stage": "synth" }
{ "type": "hdl", "stage": "program", "bitstream": "${workspaceFolder}/.hdl-studio/vivado/blink.bit", "server": "localhost:3121" }
{ "type": "hdl", "stage": "xsim", "testbench": "blink_tb" }

The task’s terminal shows the tool’s output, and the same text goes to the output channel HDL Studio: Flow, where file:line references are links. Errors and warnings land in the Problems view through the $hdl-vivado and $hdl-ghdl problem matchers. Terminating the task kills the tool and its children, so nothing keeps holding the cable.

The work folder#

Vivado always runs with <workDir>/vivado as its working directory, so nothing lands in your project folder:

synth.tcl impl.tcl bitstream.tcl program.tcl hardware.tcl open.tcl   generated scripts (edits are overwritten)
synth.log synth.jou ...                                              vivado -log / -journal of each stage
synth.dcp impl.dcp                                                   checkpoints
<top>.bit <top>.ltx                                                  bitstream and debug probes
reports/<stage>_timing.rpt _utilization.rpt _drc.rpt                 timing summary, utilisation, DRC
xsim/                                                                xvhdl, xelab and xsim working folder
status.json                                                          state of every stage, last programming

The standard of the workspace file picks the switch of read_vhdl (-vhdl2008 for 08, -vhdl2019 for 19). Testbenches are not read for synthesis. HDL Studio: Open in Vivado opens a generated project in the Vivado GUI.

Reports#

After each stage the key figures are read from the reports. The most advanced stage that wrote a report wins:

• Timing: WNS, TNS, WHS, THS and the failing endpoints.
• Utilisation: LUT, register, block RAM and DSP rows with used, available and percent.
• DRC: the violations by severity.

The Flow view shows them under Reports (“WNS 6.970 ns”, “LUT <0.01 % · FF 0.06 %”, “no violations”). A row opens the report, HDL Studio: Show Vivado Reports lists them, and hdl reports --json prints the same numbers.

xsim#

When Vivado is found, the Flow view has a row Run <testbench> with xsim. It compiles with xvhdl, elaborates with xelab and runs a Tcl batch that logs every signal to a VCD:

open_vcd "/p/.hdl-studio/blink_tb.xsim.vcd"
log_vcd *
run 1 us
close_vcd
quit

The testbench’s stop time sets run, or it runs run all when there is none. When it ends, the VCD opens in the signal viewer.

From the command line#

hdl flow synth          # or analyse, elaborate, simulate, impl, bitstream, xsim
hdl flow bitstream --json
hdl reports

examples/basys3, a blinker for the Basys 3, goes through hdl flow synth in about 30 seconds. examples/arty-a7 is the same blinker for the Arty A7-35: hdl flow bitstream takes about 60 seconds (WNS 7.21 ns, DRC clean).