FPGA flow
Synthesis, implementation, bitstream, xsim and programming with Vivado, and the block design editor.
The workspace file is the project: its part and board, top, sources, constraints, workDir and testbenches drive every stage. The Flow and Hardware views, the hdl tasks and the hdl flow, hdl program and hdl reports commands all run the same plans.
The Vivado flowRun synthesis, implementation, bitstream and xsim as VS Code tasks, and read timing, utilisation and DRC.
Programming the boardThe Hardware view, hw_server, programming and verifying a device.
Block designsWire entities, Xilinx IP and primitives on a canvas; generate an HDL wrapper or Vivado Tcl. Files merge cleanly in git.