Soft Forge HDL Studio
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Block designs

Wire entities, Xilinx IP and primitives on a canvas; generate an HDL wrapper or Vivado Tcl. Files merge cleanly in git.

A block design wires your entities, Xilinx IP and primitives into a top level. It is drawn on a canvas, edited from the shell with hdl bd, and turned into a VHDL wrapper for GHDL or a Tcl script for Vivado’s IP integrator.

Create one with HDL Studio: New Block Design (also on a folder in the Explorer) or hdl bd create design_1.vbd.

The editor#

design_1.vbd: Auto-Layout, fit, Validate, then Generate HDL Wrapper.
  • A toolbar with add block, add port, zoom, fit, validate, layout and export, and on the right the validation state and the part.
  • An IP catalog / user modules pane: user modules are the entities with ports found in your workspace sources.
  • The canvas, where cards snap to an 8 px grid, inputs sit on the left and outputs on the right, and nets are routed orthogonally.
  • A Properties pane: name, parameters, ports with their nets, and Generate HDL wrapper.
Input Does
drag a card moves it
drag from a pin to a pin connects them
drag a catalogue row onto the canvas, or double-click it adds a block
click a net selects it
Delete removes the selection
Ctrl+wheel, + / - zoom
F fit

Auto-layout runs ELK (layered, left to right). A refused connection shows its reason in the Properties pane, and the design’s problems are listed in a banner over the canvas. Every edit is a document edit, so Ctrl+Z undoes it.

The catalogue#

Kind
ip clk_wiz 6.0, axi_gpio 2.0, axi_uartlite 2.0, axi_interconnect 2.1, microblaze 11.0, proc_sys_reset 5.0, blk_mem_gen 8.4
primitive BUFG, IBUFDS, constant, concat, slice, and, or, xor
entity your entities with std_logic, std_logic_vector, unsigned or signed ports

Bus ports (AXI4-Lite, GPIO, UART, LMB, BRAM) are interfaces: one pin that carries a protocol, connected to a pin with the same protocol.

A file that merges#

A .vbd is a JSON event log with one event per line. The design is the replay of the events, so two branches that each add a block produce two added lines, and git merges them without a conflict.

json
{
  "format": "hdl-blockdesign/1",
  "events": [
    {"seq":1,"at":"2026-10-10T22:59:47.262Z","by":"cli","op":"design.update","name":"design_1","part":"xc7a35tcpg236-1"},
    {"seq":2,"at":"...","by":"cli","op":"port.add","port":{"name":"sys_clk","dir":"in","width":1,"kind":"clock"}},
    {"seq":4,"at":"...","by":"user","op":"block.add","id":"b1","name":"clk_wiz_0","kind":"ip","ref":"clk_wiz","generics":{"USE_RESET":"false"},"ports":[]},
    {"seq":9,"at":"...","by":"user","op":"net.add","id":"n1","source":{"port":"sys_clk"},"sinks":[{"block":"b1","port":"clk_in1"}]},
    {"seq":20,"at":"...","by":"user","op":"view.move","id":"b1","x":264,"y":56}
  ]
}

Every operation is validated before it is written: names, widths, directions, a second driver on an input, and mismatched interfaces are all refused. A refused edit is never written, so neither the editor nor the CLI can corrupt a file. Block positions are view.move events in the same file, and a drag is coalesced into one line.

Generated files#

HDL wrapper (<design>_wrapper.vhd, Generate HDL Wrapper): an entity with the external ports, a signal per net and an instance per block. User modules are instantiated directly; IP, BUFG and IBUFDS go through component declarations; constant, concat, slice and the logic gates become concurrent assignments. No text is produced while the design has errors.

Vivado (<design>.bd.tcl, Export Block Design to Vivado): create_bd_design, the cells with their VLNV and CONFIG.* properties, ports, nets, validate_bd_design, save_bd_design and make_wrapper. Source it in a project with vivado -mode batch -source design_1.bd.tcl.

From the command line#

sh
hdl bd create design_1.vbd --part xc7a35tcpg236-1
hdl bd port design_1.vbd sys_clk in
hdl bd add design_1.vbd ip:clk_wiz --name clk_wiz_0 --generic USE_RESET=false
hdl bd add design_1.vbd entity:counter --name counter_0 --generic WIDTH=8
hdl bd connect design_1.vbd sys_clk clk_wiz_0.clk_in1
hdl bd connect design_1.vbd counter_0.count led
hdl bd layout design_1.vbd
hdl bd validate design_1.vbd
hdl bd wrapper design_1.vbd
hdl bd export-vivado design_1.vbd

An editor that has the file open picks up each change, as it would a git pull. See The hdl command line.

Documentation for HDL Studio 1.0.4.