Panelization

A panel is a .kicad_panel file (JSON) next to the boards it uses: the boards, a grid (columns × rows, gaps, alternate 180° rotation) or manual instance positions, rails (top / bottom / left / right in mm) with fiducials and tooling holes, the separation of rows and columns (V-score, mouse bites, tabs or none) and the rail text. Electronics Designer: New panel (or Panels in the Project view, or edsnx panel new) asks for the board and the grid and writes <name>.kicad_panel; the default is 3 × 2, V-scored rows, mouse-bite columns, 8 mm rails, three fiducials and four 3 mm tooling holes.

Opening the file shows the generated panel board in the board view with the Panel tab: Boards (Add board…, remove), Layout, Rails, Separation (mouse bites: hole Ø, pitch, holes per tab, tab width, tabs per edge), Text, the summary (size, boards, tabs, holes, V-scores, fiducials, tooling, warnings) and the actions Generate, Export panel, Gerbers and Panel DRC. Every field is one undo step. The Instance tool drags a board of the panel (a grid becomes a manual layout, keeping the positions), R turns the one under the cursor by 90° and F mirrors it. With a manual layout the Layout section lists the instances, each with a Mirrored checkbox ("mirror": true on the instance in the file).

Generate writes panel/<name>.kicad_pcb and its .kicad_pro (the board’s design rules and net classes), a plain KiCad board:

• every instance is a full copy of its board (footprints, tracks, vias, zones, graphics), rotated and moved; references are kept, and a hidden Panel.Instance field on each footprint says which instance it belongs to;
• a mirrored instance is turned over like KiCad’s Flip: front and back layers swap (inner layers in reverse order), footprints go to the other side, texts read mirrored, and the copy is mirrored left to right in its box;
• zones are refilled after the copy (options.refill, on by default): each instance’s zones are first clipped to its outline less the board’s copper-to-edge clearance, so fills stay clear of the V-scores and milled edges;
• a release stamp on the board (see Output jobs and releases) is left out of the copies; the panel gets one;
• nets are prefixed per instance: GND becomes P1/GND, /LED_A becomes /P1/LED_A, so instances are separate nets for DRC and the IPC-D-356 netlist; net-class assignments follow;
• the panel outline is the union of the boards, the rails and the tabs, minus the milled slots, on Edge.Cuts;
• V-scores are lines on User.Comments with a “V-SCORE” label; mouse bites, fiducials and tooling holes are footprints (Panel_MouseBites_…, Panel_Fiducial_…, Panel_Tooling_…) excluded from the BOM and position files;
• the panel description is kept in the board as the softforge.panel property, which the panel DRC reads.

Panel DRC runs the board DRC on the panel board plus four panel rules (Board Setup ▸ Violation severity): panel_board_to_rail (board edge to rail, overlaps), panel_mousebite_copper (copper near a mouse-bite hole), panel_fiducial_clearance (copper or holes in a fiducial’s keep-out) and panel_vscore_copper (copper near a V-score line). The limits are the panel’s options: 0.5, 0.25, 1.5 and 0.4 mm by default.

edsnx panel new examples/sample-project/blinky.kicad_panel --boards examples/sample-project/blinky.kicad_pcb
edsnx panel set blinky.kicad_panel --layout '{"cols":4}' --separation '{"cols":{"kind":"mousebites","count":6}}'
edsnx panel drc blinky.kicad_panel --engine both
edsnx panel export blinky.kicad_panel --gerbers fab/

The sample project has blinky.kicad_panel and its generated panel/blinky-panel.kicad_pcb (154 × 86 mm, 6 boards, 8 mouse-bite tabs, 3 V-scores), which passes kicad-cli DRC with no violations.