DFM profiles

A DFM profile is a fabricator’s capability sheet as JSON: fab limits (track width, clearance, drill range, annular ring, via diameter, mask dam and expansion, silk width and silk to pad, copper to edge, hole to hole and to copper, board thickness, aspect ratio, via in pad, slot width, board size), assembly spacing by package class pair ("0402|0603": 0.2, "BGA|*": 0.5, "*|*": 0.25), an edge keep-out, the gap between a tall part and a short one, single-sided assembly, and test access (probe pad, pitch, side, minimum access %).

Bundled profiles: JLCPCB 2, 4 and 6-layer, PCBWay standard, OSH Park 2-layer, Eurocircuits standard pool and Aisler 2-layer. Their values are typical figures from each fab’s published capability page and every limit says “typical, verify”: check the current page before you order. Your own profiles are *.dfm.json files in the project folder (or any .json in its dfm/ folder), or profiles imported into the .kicad_pro (softforge.dfm.profiles). The project’s active profile is softforge.dfm.active; without one the bundled profile matching the board’s copper layer count is used.

The DFM tab (right side of the board editor) picks the fabricator, lists each limit with this board’s result (✓, or the number of findings in warning or error colour) and has Run DFM, Import profile (a JSON file, made the active profile) and Save as pack, which writes the profile’s hard limits as the Constraint Manager’s DFM: … rules into the .kicad_dru, so KiCad’s own DRC (and kicad-cli) enforces them too. After a first run the check re-runs on every edit. Findings appear in the Checks tab under a DFM group titled with the profile (rows grouped DFM / DFA / DFF; a click selects the items and centres the marker), as markers on the board and in the Problems panel. Board Setup ▸ Constraints ▸ Manufacturing (DFM) has the same profile picker with Use profile limits (fills the pack from the profile) and Run DFM.

Via in pad is a policy per profile ("viaInPad": "allowed" | "warn" | "forbidden" at the top of the profile): forbidden gives a dfm_via_in_pad error, warn a warning (filled and capped vias cost extra), allowed no finding. Bundled: forbidden for JLCPCB 2-layer, OSH Park and Aisler, warn for JLCPCB 4-layer, PCBWay and Eurocircuits, allowed for JLCPCB 6-layer. The DFM tab’s Via in pad row has a selector that overrides the policy for this project (softforge.dfm.viaInPad in the .kicad_pro), the same as edsnx dfm via-in-pad set warn --profile jlcpcb-2 (default removes the override). schemas/dfm-profile.schema.json validates *.dfm.json files in the editor.

The assembly checks measure the real part shapes: the courtyard polygon (any shape, turned with the part), else the convex hull of the part’s Fab graphics, else of its pads. Spacing (dfa_spacing, dfa_tall_near_short) is the gap between those shapes, so a part may sit in the notch of an L-shaped courtyard, and the edge keep-out uses the same shapes.

Rule ids: dfm_track_width, dfm_clearance, dfm_drill, dfm_annular_ring, dfm_via_diameter, dfm_mask_sliver, dfm_mask_expansion, dfm_silk_width, dfm_silk_to_pad, dfm_copper_to_edge, dfm_hole_to_hole, dfm_hole_to_copper, dfm_aspect_ratio, dfm_via_in_pad, dfm_slot_width, dfm_board_thickness, dfm_board_size, dfa_spacing, dfa_edge_keepout, dfa_tall_near_short, dfa_same_side, dff_test_access, dff_test_pitch. Hard fab limits are errors, the rest warnings; rule_severities in the .kicad_pro changes them like any DRC rule.

Silkscreen width (dfm_silk_width, a warning) is reported once per library footprint, not per line: KiCad’s libraries draw silk at 0.12 mm and texts at 0.15 mm, below the 0.153 mm (6 mil) most fabs publish, so the sample gives “Silkscreen line width of 8 lines in Capacitor_SMD:C_0805_2012Metric (C1, C2, C3, C4)” and one such line per package instead of a warning for every line. Board-level silk graphics are still reported one by one. Fabs usually print thinner silk anyway, only less crisply: raise the library’s width or accept the warning.

edsnx dfm run --profile jlcpcb-4             # the sample: 0 errors, silk warnings
edsnx dfm profiles list
edsnx dfm profiles import --file myfab.dfm.json --activate
edsnx dfm profiles export jlcpcb-4 --out myfab.dfm.json
edsnx dfm profiles activate oshpark-2
edsnx dfm save-pack --profile jlcpcb-2