Test points

Check that every net can be probed and add test pads where it cannot.

The Test tab (board editors) checks that every net can be probed and adds test pads where it cannot. The rules are kept in the .kicad_pro (softforge.testPoints): nets (all, signals without power nets, or a list of globs), excluded nets, minimum pad size (0.8 mm), minimum probe pitch (1.27 mm), side (top, bottom, either) and whether pads or vias are preferred. Existing copper is used first: SMD and through-hole pads with a mask opening on the probed side, TestPoint footprints first, then through vias that are not tented. Nets without access get a TestPoint_Pad_D… footprint (Auto-assign): on their own track or zone where there is room, else at the end of a short stub track (up to 8 mm) from one of the net’s pads, vias or tracks, else where another net’s zone fill gives way (the zones are refilled after placing). Every spot is clear of other copper, holes, courtyards and the board edge, at the probe pitch from the other points, and the placed board passes DRC. A net that still cannot be reached is listed with the reasons its candidate spots were refused (clearance, courtyard, hole, edge, pitch …).

IPC-D-356 writes the bare-board test netlist (the same records as kicad-cli, with test points only on request) and Probe report writes a probe CSV, a flying-probe CSV and a Takaya-style text file, with coordinates from the board’s lower-left corner.

sh
edsnx test report blinky.kicad_pcb --existing
edsnx test rules set blinky.kicad_pcb --rules '{"side":"bottom","pitchMin":2.54}'
edsnx test assign blinky.kicad_pcb --place
edsnx test ipcd356 blinky.kicad_pcb --out fab/blinky.ipc
edsnx test probe-report blinky.kicad_pcb --format flying

Documentation for Electronics Designer 2.3.60.