Board setup
Layers, the physical stack-up, net classes, constraints and custom rules.
Electronics Designer: Board Setup… (editor title bar ▸ …) opens KiCad’s Board Setup dialog: board editor layers,
physical stack-up, board finish, solder mask/paste, text and graphics defaults, constraints, pre-defined
track widths and via sizes, net classes (with net patterns), custom rules and violation severities.
Apply writes the board file and the .kicad_pro; the whole change is one undo step.
Design Rules ▸ Teardrops sets the teardrop shapes KiCad uses when it adds and regenerates teardrops: which items
get them (vias, PTH pads, SMD pads, track ends, round shapes only) and, for round shapes, rectangular shapes and
track-to-track joints, the best and maximum length and width, curve points, the largest track-to-pad width ratio,
two-segment teardrops and pads inside zones. Design Rules ▸ Length-tuning Patterns sets the defaults of new
tuning patterns for single tracks, differential pairs and differential pair skew: minimum and maximum amplitude,
spacing, corner style and radius, single-sided. Both pages are stored in the .kicad_pro as KiCad stores them
(teardrop_options, teardrop_parameters, tuning_pattern_settings); keys the pages do not show are kept.
Teardrops added with Route ▸ Add Teardrops survive KiCad: their pads and vias are marked
(teardrops … (enabled yes)) (KiCad 9 and later boards) and track-end teardrops switch on the project’s
td_track_end parameters, so a zone refill in KiCad or kicad-cli pcb drc --refill-zones regenerates them
instead of deleting them. Removing teardrops switches their pads and vias off again.
Pages added by the extension: Board Stackup ▸ Stack-up Regions and Via Spans (Rigid-flex and HDI), the Constraints pages (Physical, Spacing, Electrical, Manufacturing (DFM), Rules, Impedance) and Constraint Layers.
Layer stack view#
The Layer stack view (right side, board documents) plans the stack-up beside the board. Its grid lists every stack-up row: layer, type, material, thickness, εr, loss tangent, copper weight, colour and whether the layer is enabled, with the total thickness from the stack-up against the board thickness (Set board thickness from stack-up when they differ). Arrow keys move between cells, Enter or F2 edits, Enter or Tab commits and Esc cancels; each commit writes the Board Setup stack-up as one undo step (a copper weight in oz sets the copper thickness, 1 oz = 35 µm). Below the grid, Reference traces gives per signal layer the width of a 50 Ω single-ended trace and the width and gap of a 100 Ω differential pair (outer layers as microstrips, inner layers as striplines, the same formulas as the Impedance page; the pair gap is the dielectric height, at least the minimum clearance). Via spans and Stack-up regions are read-only. Each section links to its Board Setup page (Physical Stackup, Impedance, Via Spans, Stack-up Regions), where dielectrics are added and the copper count, spans and regions change.