Signal and power integrity

The SI/PI tab on the right of a board editor (command softforge.edsnx.si.show, edsnx si show-panel) estimates signal integrity per net and solves the DC power distribution. Its settings, models, points and last results are kept in <board>.kicad_si.json next to the board; the editor creates it with the first edit. The design note is the board section ANA-4.

Signal integrity · per net. Recompute analyses every routed signal net (not the power and ground nets):

Click a row to select the net’s tracks. IBIS models picks a driver and receiver model and pin per net from the built-in set (CMOS 3.3 V / 5 V / 1.8 V / 1.2 V, LVDS, SSTL-1.5, a 5 pF input) and the SI file’s ibis list (edsnx si set --models, or an .ibs file). Reflections then simulate the net’s sections with the driver into the receiver. A model read from an .ibs file with its tables drives the simulation with them: the pull-up and pull-down V-I tables, the power and ground clamps and the rising / falling V-t waveforms (the switching coefficient is recovered from the waveform and its test fixture), solved at every time step against the line; models without tables use the output resistance and edge rate into the receiver’s input capacitance. Export table saves both tables as CSV.

Lossy, dispersive lines. The sections are lossy transmission lines built from the stack-up (2.1.0): conductor loss with the skin effect (Wheeler’s incremental inductance, a causal internal impedance, copper roughness roughnessUm) and dielectric loss with a Djordjevic–Sarkar model of the laminate’s εr and loss tangent (tanD, default 0.02 at 1 GHz). R, L, G, C follow from them per frequency; the reflection simulation convolves each section’s causal impulse response, so edges slow down and round off with length. Hover a net for its insertion loss at fMaxHz (conductor and dielectric parts). The model matches the closed-form attenuation of Pozar / Gupta–Garg–Bahl from 0.1 to 10 GHz: stripline conductor loss within 2 %, microstrip within 7 % for w/h ≥ 0.75 (16 % at w/h = 0.5, where the closed form itself is weakest), dielectric loss within 3.1 %. edsnx si lossy lists R, L, G, C, attenuation and delay per frequency for a layer and width, or for a net, and writes the net’s S-parameters (--out net.s2p). Rule lossy: true in the SI file turns the lossy sections on in the reflection model (off by default: the live DRC runs this analysis on every pass, and the lossy convolution costs about half a second on the sample board); edsnx si lossy always computes the lossy line.

Power integrity · PDN. Add source and load points on pads: the Add Load Point tool (button Add load point) adds a 0.1 A load on the clicked pad’s net, Shift+click adds a source with the voltage from the net name (+3V3 → 3.3 V, GND → 0 V). Edit currents and voltages in the list under the table. Solve DC builds a resistive mesh of each supply net’s zone fills (a grid), tracks, vias and pads and solves it; the table shows per net the total load, the worst drop against its limit (✓ / ✗; rule irDropMaxMv per net, default 5 % of the source voltage or 10 mV on ground) and the worst current density. When you add, remove or edit a point after a solve, the drop and J columns turn grey and say stale until the next Solve DC. Two heat overlays appear per net (si.pdn.<net>.drop in mV and si.pdn.<net>.j in A/mm²; Custom tools and overlays shows them like any other field). On a ground net whose sources are 0 V, the loads return their current. Decoupling check finds the nearest capacitor between each IC’s supply pin and ground and estimates the loop inductance. As requirement adds a requirement “IR drop of the net ≤ its limit” on the drop overlay, evaluated live (see Requirements and solving).

PDN impedance (AC). AC impedance (2.1.0, edsnx si ac) computes |Z(f)| of each supply net seen from an IC’s supply pins, from 10 kHz to 1 GHz by default: the voltage regulator (R + L), every decoupling capacitor with its ESR, ESL and mounting inductance (from the part’s ESR / ESL fields when present, else from the package size), the spreading inductance to the IC, the plane pairs with their plane-to-plane capacitance (ε0·εr·A / h of the overlapping supply and ground fills) and the first cavity resonance. A row per net gives the plane capacitance and the |Z| range against the target impedance (Zt = V × ripple / (I × step fraction), rule pdnAc); click it for the |Z(f)| chart with the target mask (red where |Z| is above it). The AC solve is on demand and does not slow down the DC solve.

Radiated-emission estimate. Estimate emission (2.1.0, edsnx si emission) estimates the far field of the clock and signal nets: the differential-mode loop of each net (area from the track and its return path) and the common-mode current where the return path is broken (the si_return_path_split and si_reference_change_no_via findings, and an attached cable cableM), with the trapezoidal spectrum of each net’s edge (toggle frequency clocks, default defaultClockHz). The chart — labelled ESTIMATE — shows the total, the differential and the common-mode envelopes against the CISPR 32 class B limit (10 m, quasi-peak); the panel row gives the worst margin. It is an estimate from closed-form models (Ott): it ranks the risks and shows what a fix changes; it is not a measurement.

Return path and EMC. These DRC rules run with the live checks when the board has an SI file, and show in the Checks tab and in this list (click to reveal):

Rules (fold-out at the bottom of the panel) edits these settings; edsnx si set --rules does the same.

S-parameters and field solvers. Open .sNp… reads a Touchstone file (v1 or v2) into the S-parameter card over the canvas: S21 and S11 in dB against GHz, chips to show other Sij, and the −3 dB / −10 dB points in its title. Hand-off… writes a model of the selected nets for a field solver: openEMS (a Python script for CSXCAD / openEMS that writes <name>.s2p, and geometry.xml for AppCSXCAD) or Elmer (model.geo for gmsh, case.sif, run.sh). The region is the nets’ copper plus 3 mm with the reference planes in it; the mesh preset sets 10 / 20 / 40 cells per wavelength at f max; lumped 50 Ω ports go on the two farthest pads of each net. The openEMS model has voltage and current probes at each port.

Running the field solvers. With openEMS or Elmer installed (2.1.0), the Tools view has two runnable custom tools, openEMS · S-parameters of the net and Elmer · E field of the net, and edsnx si solve --tool openems|elmer runs them: the hand-off is written, the solver runs, and the result comes back — openEMS’s port probes become S-parameters in the S-parameter card, Elmer’s VTU result becomes a field overlay. edsnx si solvers reports what is installed. When a solver is missing (or broken: an openEMS binary that cannot load its libraries counts as missing) the tool is labelled (not installed) with the reason and what to install, and the command fails with that note instead of running; nothing else changes. The examples examples/tools/openems-antenna and examples/tools/elmer-thermal also detect their solver (--detect, --require-solver). From the command line:

edsnx si tline board.kicad_pcb                       # Z0, delay, crosstalk, reflections per net
edsnx si point add board.kicad_pcb --ref U1 --pad 8 --current-a 0.3
edsnx si pdn board.kicad_pcb --out si-fields         # IR drop, J, decoupling; field JSON files
edsnx si checks board.kicad_pcb                      # the SI / PDN DRC rules alone
edsnx si handoff board.kicad_pcb --tool openems --nets CLK --out em/
edsnx si sparams em/CLK.s2p
edsnx si lossy board.kicad_pcb --net CLK --out clk.s2p   # RLGC, loss and the net's S-parameters
edsnx si ac board.kicad_pcb --nets +3V3                # PDN |Z(f)| against the target impedance
edsnx si emission board.kicad_pcb --clocks '{"CLK": 25e6}'
edsnx si solvers                                     # openEMS / Elmer installed?
edsnx si solve board.kicad_pcb --tool openems --nets CLK --out em/

The sample project has an SI file with +5V and GND sources and loads, NE555 output models on /OUT and a synthetic si/out-line.s2p. These are estimates: closed-form impedance and crosstalk, a lossy line model, lumped PDN impedance and a closed-form emission estimate; use the field solvers for sign-off.