Live checks: ERC and DRC

The design is checked while you draw it. A native DRC (boards) and a native ERC (schematics) run after every edit, undo and redo, with the same rule ids, severities, exclusions and positions as kicad-cli 10, so a design that is clean here is clean in KiCad (see the parity tables in live-checks.md).

How live checks run#

• Opening a board runs a full DRC; opening any sheet of a project runs a full ERC over the whole hierarchy (every sheet, the unsaved text of open sheets first).
• Each edit is checked incrementally: only the items it touched, their neighbours and their nets (DRC) or the sheets whose text changed (ERC). Edits within softforge.edsnx.liveChecks.debounceMs (150 ms) are coalesced; a newer edit cancels the pass in flight. The engines run in a worker thread, so the editor never waits for them. Board Setup, net class, custom rule, project file and library table changes run a full pass.
• While a pass runs the Checks panel shows a stale badge. Electronics Designer: Run live checks (full native pass) forces a full pass; Electronics Designer: Run full DRC/ERC (kicad-cli) (or Run DRC / Run ERC / Run checks) runs kicad-cli on the current text. Its results are merged with the native ones into one list; each row shows where it came from (native, kicad-cli, both) and the header says when both agree.
• Library rules (lib_footprint_issues, lib_footprint_mismatch, lib_symbol_issues, lib_symbol_mismatch, footprint_link_issues) use the project’s and the global library tables, like KiCad.
• Schematic ↔ board parity (missing or extra footprints, value and net differences) is checked live from the project’s netlist when the board has a schematic (softforge.edsnx.liveChecks.parity).
• softforge.edsnx.liveChecks.enabled: false turns the native checks off; kicad-cli runs still work.

Markers, the Checks panel and Problems#

• Every violation is a marker on the canvas (errors red, warnings amber); hover a marker for the rule, the message and the items. The status strip shows ERC n · DRC n · unrouted n and the VS Code status bar the counts of the active project (click: Show checks).
• The Checks tab lists the violations grouped by rule, with filters by severity, rule, net, layer, sheet and text. Click a row to select and centre its items; on a schematic, a violation on another sheet opens that sheet.
• The Problems panel has one diagnostic per violation on its file; Show in the editor jumps to it.

Quick fixes#

The light bulb on a marker or a Checks row (and the code action in Problems) offers the fixes for the rule:

A fix is an ordinary edit: Ctrl+Z undoes it.

Exclusions and severities#

• Exclude asks for a reason (optional) and writes the exclusion to the .kicad_pro the way KiCad does (drc_exclusions, erc_exclusions; KiCad 9+ stores the note next to the key), so pcbnew, eeschema and kicad-cli honour it. Excluded rows stay in the list, dimmed, with their note; Include removes the exclusion. Exclusions are undoable edits and are saved with the document.
• The severity of a rule (error / warning / ignore) can be changed from its group header in the Checks tab or in Board Setup ▸ Violation Severity; it is stored in rule_severities of the .kicad_pro.

Constraint Manager and custom rules#

Board Setup ▸ Constraints edits the design rules as tables: Physical (net class sheet and per-net overrides of width, via and clearance), Spacing (net class × net class clearance matrix), Electrical (diff pair, length, skew, via count per class), Manufacturing (DFM) (a pack of fabrication rules to switch on one by one) and Rules (the raw <board>.kicad_dru with highlighting, live diagnostics, templates and a test against the selection). Constraint Manager entries are written as CM: … rules into the .kicad_dru; other rules in the file are left alone. The live DRC uses the rules as soon as they are applied (or the file changes on disk); a violation caused by a custom rule names it (rule 'CM: …') and its Open the rule fix goes to the Rules page. As in KiCad, a rules file with errors is ignored as a whole until they are fixed (the Problems panel lists them). A rules change made from these pages is one step of the board’s undo history: Ctrl+Z in the editor (or Electronics Designer: Undo/Redo Last Custom Rules Change) restores the previous file.

Custom rules editor#

A .kicad_dru opened as text is the Custom Design Rules language: syntax colouring of clauses, constraint names, units, severities and the condition expressions, diagnostics in the Problems panel while you type, and completions: clause keywords after (, every constraint name after (constraint (with its value kind), the board’s layer names (and outer / inner) after (layer , severities, min / opt / max, disallow item types and zone connections; inside a condition string the A. / B. properties, functions, item types and the board’s net classes, nets and layers in quoted literals. Hovering a constraint or clause explains it. As in KiCad, track_angle takes plain degrees ((min 120)): a unit there is an error, because KiCad would ignore the whole file.

Constraint rules checked live#

The live DRC (and edsnx check) evaluates the custom-rule constraints KiCad 10 checks, with kicad-cli’s messages:

While zones need a refill after an edit, copper_sliver is checked on the copper the next fill will make (the zones are refilled in memory with the same filler as Fill All Zones), not on the outdated stored fill. The ERC reports a wire ending on a bus without a bus entry (bus_entry_needed) and reads the SPICE model files a symbol names (Sim.Library, Sim.Name, .include followed): a missing library or model is simulation_model_issue, as in kicad-cli.

Checks from the command line#

edsnx check runs the same native checks outside the editor: a board (DRC), a schematic (ERC) or a project (both), one line per violation and a summary per file.

edsnx check blinky.kicad_pro --check          # CI gate: exit 1 when there are errors (--warnings: also on warnings)
edsnx check blinky.kicad_pcb --watch          # re-run on every change; later runs print + new / - fixed only

--watch re-runs whenever a board, schematic, rules or project file of the folder changes (--runs n stops after n runs); --json prints one JSON object per run with the added and fixed violations.

Design health and output gating#

Electronics Designer: Design health summarises the project: ERC, DRC, unrouted connections and parity, with counts and when they last ran. Plot, drill and position files, 3D exports and the BOM check it first (softforge.edsnx.outputs.gate):

• warn (default): a warning when checks have errors or are out of date, the output is still written;
• block: the output is not written until the checks are clean (or excluded);
• off: no gate.

Board outputs need a clean DRC, the BOM a clean ERC (open the schematic to check it live, or run ERC).

Settings#